The present invention relates to a semiconductor integrated circuit device provided with equalizing pulse generating circuits.
In prior-art semiconductor integrated circuit devices (referred to as IC, hereinafter), that is, in static LSI memory devices in particular, an equalizing pulse generating circuit is provided for increasing data read speed from memory cells. The above-mentioned equalization is effected as follows: an equalization transistor is provided between a pair of bit lines b; address transition detectors are provided to detect a change in address; a plurality of the address transition detection signals are synthesized by an equalizing pulse generating circuit composed of logical circuits to generate an equalizing signal which can turn on the equalization transistor to equalize the voltage levels of the two bit lines.
In designing the equalizing pulse generating circuit for equalizing the bit lines in level as described above, the following points must be taken into account:
(1) The logical circuits constituting the equalizing pulse generating circuit must be combined efficiently so that the level of the bit lines is equalized on the basis of pulse signals generated by the address transition detectors and a control circuit. In addition, the number of stages of the logical circuits must be minimized; PA1 (2) The optimum dimensions must be determined for the respective logical circuits under due consideration of the wire capacitance, the gate capacitance of the succeeding stage, etc.; and PA1 (3) The pattern of the logical circuits formed on a chip must be optimized so that the lengths of wires from the address transition detectors and the control circuit to the logical circuits can be minimized. PA1 (a) The equalizing pulse signals are generated from the equalizing pulse generating circuit composed of combined logical circuits, on the basis of change in address detected by all the address transition detectors. Therefore, there exists such a tendency that the scale of the equalizing pulse generating circuit increases with an increasing number of address inputs and the advance of the memory capacities, with the result that it has become difficult to further reduce the number of stages of the logical circuits for improvement of the data read speed to the memory cells. PA1 (b) Within the chip, the number and the length of wires between the address transition detectors, the control circuit and the logical circuits inevitably increase with increasing memory capacity, as compared with those of the conventional memory device. Accordingly, since the respective output load capacitances of the respective logical circuits increase with increasing wire capacitances, the dimensions of the respective logical circuits or the inverter circuits in particular, increase. In the case where the dimensions increase, since the output load capacitance of the preceding stage logical circuit tends to drive the inverter circuit of increased dimensions, it is also necessary to increase the preceding stage circuit dimensions, thus resulting in a vicious circle. To avert this vicious circle, a method of driving the logical circuits by large dimensional circuits or the method of increasing the number of logical gates is required, thus reducing the data read speed to the memory cells. PA1 (c) With respect to the peripheral circuits, there exists a tendency that the number of stages of the logical circuits from address inputs to word lines WL connected to the memory cells decreases due to miniaturization of the device or formation of the circuits into BiCMOS devices. In contrast with this, since the number of logical stages of the equalizing pulse circuit for generating an equalizing pulse signal does not change or tends to be increased for the reason as described in items (a) and (b) above, there exists a problem in that only the speed of equalization is not increased. PA1 The above-mentioned problem will be explained in more detail with reference to FIG. 5, which shows an arrangement on a prior-art semiconductor IC device chip. In FIG. 5, address transition detectors ATD.sub.i (i=1, . . . 7) and a control circuit CC are arranged on predetermined positions on the chip in such a way that the detectors ATD.sub.4 . . . ATD.sub.7 are formed on the left side of the memory cell section; the detectors ATD.sub.2 and ATD.sub.3 are formed on the upper side of the memory cell section; and the detector ATD.sub.1 and the control circuit CC are formed on the right side of the memory cell section. Further, logical circuits 50 . . . 60 which constitute an equalizing pulse generating circuit are arranged at appropriate positions under due consideration of the afore-mentioned items (1), (2) and (3). Input nodes 301, . . . 308 of NAND gates 50, . . . 53 are roughly equal to each other in wire length and therefore there exists no specific problem. However, only an input node 311 to a NOR gate 55 is longer in wire length than other input nodes 309, 310, and 312 to NOR gates 54 and 55. Further, an input node 314 to a NAND gate 56 is much longer in wire length than an input node 313 to the same NAND gate 56, thus resulting in an unbalanced wire layout.
With the advance of the larger capacity and higher speed static memory devices, recently, the following problems arise in designing the above-mentioned equalizing pulse generating circuit.
When a pair of nodes to be compared is in unbalanced condition; that is, when one of the node wire lengths is longer than the other node wire lengths, the capacitance of the long node wire is larger than that of the short node wire. For instance, the wire capacitance of the node 311 is large, and the wire capacitances of the nodes 309, 310, and 312 are roughly equal to each other and small in comparison with that of the node 311. Therefore, even if the circuit dimensions of the NAND gates 50, . . . 53 are all the same, since only the NAND gate 52 whose output terminal is connected to the node 311 has a large wire capacitance as compared with those of the other NAND gates 50, 51 and 53, a problem arises in that the operation speed of the equalizing pulse generating circuit composed of the logical circuits is inevitably reduced.